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mas 3507d mpeg 1/2 layer 2/3 audio decoder edition march 1 6 , 2000 6251-459-3pd preliminar y d a t a sheet micr onas
mas 3507d preliminary data sheet 2 micronas contents page section title 5 1. introduction 5 1.1. features 6 1.2. application overview 6 1.2.1. multimedia mode 6 1.2.2. broadcast mode 7 2. functional description of the mas 3507d 7 2.1. dsp core 7 2.2. firmware (internal program rom) 8 2.3. program download feature 8 2.4. baseband processing 8 2.4.1. volume control / channel mixer 8 2.4.2. mute / bypass tone control 8 2.4.3. bass / treble control 9 2.5. clock management 9 2.6. power supply concept 9 2.6.1. internal voltage monitor 9 2.6.2. dc/dc converter 9 2.6.3. stand-by functions 10 2.6.4. start-up sequence 11 2.7. interfaces 11 2.7.1. mpeg bit stream interface (sdi) 11 2.7.2. sdi* selection 12 2.7.3. parallel input output interface (pio) 12 2.7.3.1. pio-dma input mode 12 2.7.3.2. writing mpeg data to the pio-dma 13 2.7.3.3. dma handshake protocol 13 2.7.3.4. end of dma transfer 13 2.7.4. audio output interface (sdo) 13 2.7.4.1. mode 1: 16 bits/sample(i 2 s compatible data format) 14 2.7.4.2. mode 2:32 bit/sample (inverted soi) 14 2.7.4.3. other output modes 15 2.8. start-up configuration 15 2.8.1. parallel input output interface (pio) 16 2.9. status pins in sdi input mode
contents, continued page section title preliminary data sheet mas 3507d micronas 3 18 3. control interfaces 18 3.1. i 2 c bus interface 18 3.1.1. device and subaddresses 19 3.2. command structure 19 3.2.1. the internal fixed point number format 20 3.2.2. conventions for the command description 20 3.3. detailed mas 3507d command syntax 20 3.3.1. run 21 3.3.2. read control interface data 21 3.3.3. write register 21 3.3.4. write d0 memory 21 3.3.5. write d1 memory 22 3.3.6. read register 22 3.3.7. read d0 memory 22 3.3.8. read d1 memory 22 3.3.9. default read 23 3.4. protocol description 23 3.4.1. run command 23 3.4.2. read control interface data 23 3.4.3. write to mas 3507d register 23 3.4.4. write to mas 3507d d0 memory 24 3.4.5. write to mas 3507d d1 memory 24 3.4.6. read register 24 3.4.7. read d0 memory 24 3.4.8. read d1 memory 25 3.4.9. default read 25 3.4.10. write data to the control register 25 3.5. version number 26 3.6. register table 26 3.6.1. dc/dc converter 28 3.6.2. muting / bypass tone control 28 3.6.3. bass and treble control 30 3.7. memory area 30 3.7.1. status memory 30 3.7.1.1. mpeg frame counter 31 3.7.1.2. mpeg status 1 32 3.7.1.3. mpeg status 2 33 3.7.1.4. crc error counter 33 3.7.1.5. number of ancillary bits 34 3.7.1.6. ancillary data 35 3.7.2. configuration memory 36 3.7.2.1. pll offset for 44/48 khz sampling frequency 37 3.7.2.2. output configuration 37 3.7.3. baseband volume matrix
mas 3507d preliminary data sheet 4 micronas contents, continued page section title 39 4. specifications 39 4.1. outline dimensions 40 4.2. pin connections and short descriptions 43 4.2.1. pin descriptions 43 4.2.1.1. power supply pins 43 4.2.1.2. dc/dc converter pins 43 4.2.1.3. control lines 43 4.2.1.4. parallel interface lines 43 4.2.1.4.1. pio handshake lines 43 4.2.1.4.2. pio data lines 44 4.2.1.5. voltage supervision and other functions 44 4.2.1.6. serial input interface 44 4.2.1.7. serial output interface 45 4.2.1.8. miscellaneous 45 4.2.2. pin configurations 46 4.2.3. internal pin circuits 47 4.2.4. electrical characteristics 47 4.2.4.1. absolute maximum ratings 47 4.2.4.2. recommended operating conditions 49 4.2.4.3. characteristics 50 4.2.4.3.1. i 2 c characteristics 51 4.2.4.3.2. i 2 s bus characteristics C sdi 52 4.2.4.3.3. i 2 s characteristics C sdo 53 4.2.4.4. firmware characteristics 53 4.2.4.4.1. input timing parameters of the multimediamode 54 4.2.4.5. dc/dc converter characteristics 55 4.2.4.6. typical performance characteristics 60 5. data sheet history
preliminary data sheet mas 3507d micronas 5 m p e g 1/2 l a ye r 2 /3 a ud i o de c od er release note: revision bars indicate significant changes to the previous edition. thi s d a t a s h e e t a ppli e s to m a s 3 5 07 d v e r s io n g 1 0 and following versions. 1. introduction the mas 3507d is a single-chip mpeg layer 2/3 audio decoder for use in audio broadcast or memory-based playback applications. due to embedded memories, the embedded dc/dc up-converter, and the very low power consumption, the mas 3507d is ideally suited for portable electronics. in mpeg 1 (iso 11172-3), three hierarchical layers of compression have been standardized. the most sophisticated and complex, layer 3, allows compres- sion rates of approximately 12:1 for mono and stereo signals while still maintaining cd audio quality. layer 2 (widely used in dvb, adr, and dab) achieves a com- pression of 8:1 providing cd quality. in order to achieve better audio quality at low bit rates (<64 kbit/s per audio channel), three additional sam- pling frequencies are provided by mpeg 2 (iso 13818-3). the mas 3507d decodes both layer 2 and layer 3 bit streams as defined in mpeg 1 and 2. the multichannel/multilingual capabilities defined by mpeg 2 are not supported by the mas 3507d. an extension to the mpeg 2 layer 3 standard developed by fhg erlangen, germany sometimes referenced as mpeg 2.5, for extremely low bit rates at sampling fre- quencies of 12, 11.025, or 8 khz is also supported by the mas 3507d. 1.1. features C serial asynchronous mpeg bit stream input (sdi) C parallel (pio-dma) input C broadcast and multimedia operation mode C automatic locking to given data rate in broadcast mode C data request triggered by demand signal in multi- media mode C output audio data delivered (in various formats) via an i 2 s bus (sdo) C digital volume / stereo channel mixer / bass / treble C output sampling clocks are generated and con- trolled internally. C ancillary data provided via i 2 c interface C status information accessible via pio pins or i 2 c C crc error and mpeg frame synchronization indicators at pins in serial input mode C power management for reduced power consumption at lower sampling frequencies C low power dissipation (30 mw @ f s 12 khz, 46 mw @ f s 24 khz, 86 mw @ f s >24khz @ 2.7 v) C supply voltage range: 1.0 v to 3.6 v due to built-in dc/dc converter (1-cell/2-cell battery operation) C adjustable power supply supervision C power-off function C additional functionality achievable via download software (celp voice decoder, adpcm encoder / decoder) fig. 1C1: mas 3507d block diagram clki clko decoded output mpeg 1/2 audio bit stream /3/ /2/ clock synthesizer serial out i 2 s serial in i 2 c risc dsp core mpeg frame sync crc error pio dc/dc converter /3/ /8+5/ /2/ serial control mas 3507d
mas 3507d preliminary data sheet 6 micronas 1.2. application overview the mas 3507d can be applied in two major environ- ments: in multimedia mode or in broadcast mode. for both modes, the dac 3550a fits perfectly to the requirements of the mas 3507d. it is a high-quality multi sample rate dac (8 khz ... 50 khz) with internal crystal oscillator, which is only needed for generating the decoder clock, and integrated stereo headphone amplifier plus 2 stereo inputs. 1.2.1. multimedia mode in a memory-based multimedia environment, the easi- est way to incorporate a mas 3507d decoder is to use its data-demand pin. this pin can be used directly to request input bit stream data from the host or memory system. while the demand pin is active, the data stream shall be transmitted to the mas 3507d. the bit stream clock should be higher than the actual data rate of the mpeg bit stream (1 mhz bit stream clock works with all mpeg bit rates). the demand signal will be active until the input buffer of the mas 3507d is filled. a delayed response of the host to the demand signal (by several milliseconds) or an interrupted response of the host will be tolerated by the mas 3507d as long as the input buffer does not run empty. a pc might use its dma capabilities to transfer the data in the background to the mas 3507d without interfering with its fore- ground processes. the source of the bit stream may be a memory (e.g. rom, flash) or pc peripherals, such as cd-rom drive, an isdn card, a hard disk or a floppy disk drive. 1.2.2. broadcast mode in environments where the bit stream is delivered from an independent transmitter to one or more receivers, the mas 3507d cannot act as master for the bit stream clock. in this mode, it synchronizes itself to the incoming bit stream data rate by a digital pll and gen- erates a synchronized digital audio sample clock for the required output sample rates. fig. 1C2: block diagram of a mas 3507d, decoding a stored bit stream in multimedia mode fig. 1C3: block diagram of a mas 3507d in a broadcast environment mas 3507d rom, cd-rom, ram, flash mem. .. dac host 3550a (pc, controller) i 2 s line out i 2 c demand signal demand clock mpeg bit stream clki clkout 14.725 mhz mas 3507d dac receiver 3550a front-end i 2 s line out clki control i 2 c l3 bit stream (fixed rate) clock 14.725 mhz clkout
preliminary data sheet mas 3507d micronas 7 2. functional description of the mas 3507d 2.1. dsp core the hardware of the mas 3507d consists of a high performance risc digital signal processor (dsp) and appropriate interfaces (see fig. 2C1). the internal pro- cessor works with a memory word length of 20 bits and an extended range of 32 bits in its accumulators. the instruction set of the dsp is highly optimized for audio data compression and decompression. thus, only very small areas of internal ram and rom are required. all data input and output actions are based on a non cycle stealing background dma that does not cause any computational overhead. 2.2. firmware (internal program rom) a valid mpeg 1/2/2.5 layer 2/3 data signal is taken as input. the signal lines are a clock line sic and the data line sid. the mpeg decoder performs the audio decoding. the steps for decoding are C synchronization, C side information extraction, C audio data decoding, C ancillary data extraction, and C volume and tone control. for the supported bit rates and sample rates, see table 3C12 on page 32. frame synchronization and crc-error signals are provided at the output pins of the mas 3507d in serial input mode. fig. 2C1: block diagram of the mpeg decoder in serial input mode sync ancillary mpeg decoder to m c mpeg bit stream digital audio output data decoder status config. reg. pio status start-up config. volume to n e control
mas 3507d preliminary data sheet 8 micronas 2.3. program download feature this is an additional feature that is not required for the mpeg decoding function. the overall function of the mas 3507d can be altered by downloading up to 1 kword program code into the internal ram and executing this code instead of the rom code. during this time, mpeg decoding is not possible. the code must be downloaded by the write to mem- ory command (see section 3.3.) into an area of ram that is switchable from data memory to program mem- ory. a run command (see section 3.3.1.) starts the operation. micronas provides modules for voice-decoding using the celp algorithm (performing good speech quality at very low bit rates) and for encoding and decoding audio data with adpcm. detailed information about downloading is provided in combination with the mas 3507d software develop- ment package from micronas. for commercial issues and detailed information please contact our sales department. 2.4. baseband processing 2.4.1. volume control / channel mixer a digital volume control matrix is applied to the digital stereo audio data. this performs additional balance control and a simple kind of stereo basewidth enhancement. the 4 factors ll, lr, rl, and rr are adjustable via the controller with 20-bit resolution. see fig. 3C2 and section 3.7.3. for details. 2.4.2. mute / bypass tone control a special bit enables a fast and simple mute functional- ity without changing the current volume setting. another bit allows to bypass the complete bass / treble / volume control. see for details section 3.6.2. 2.4.3. bass / treble control tone control is implemented in the mas 3507d. it allows the control of bass and treble in a range up to 15 db, as table 3C9 shows. to prevent overflow or clipping effects, the prescaler is built-in. the prescaler decreases the overall gain of the tone filter, so the full range up to +15 db is usable without clipping. due to the different frequency ranges in mpeg 1, mpeg 2, or mpeg 2.5, the bass cutoff frequencies dif- fer. for details see section 3.6.3.. table 2C1: cutoff frequencies cutoff bass treble mpeg 1 100 hz 10 khz mpeg 2 200 hz 10 khz mpeg 2.5 400 hz 10 khz
preliminary data sheet mas 3507d micronas 9 2.5. clock management the mas 3507d should be driven by a single clock at a frequency of 14.725 mhz. it is possible to drive the mas 3507d with other reference clocks (see section 3.7.2.1. on page 36). the clki signal acts as a reference for the embedded clock synthesizer that generates the internal system clock. based on the reference input clock clki , a syn- chronized output clock clko that depends on the audio sample frequency of the decompressed bit stream is generated and provided as master clock to external d/a converters. some of them need master clocks that have a fixed relation to the sampling fre- quencies. a scaler can be switched on during start-up, o p ti o na l l y , b y s e tt in g the pi 8 p i n to 0 . t h en, the c l o c k - o u t will automatically be divided by 1, 2, or 4 as defined in ta b l e 2 C 2 . 2.6. power supply concept the mas 3507d offers an embedded controlled dc/ dc converter for battery based power supply con- cepts. it works as an up-converter. 2.6.1. internal voltage monitor an internal voltage monitor compares the input voltage at the vsens pin with an internal reference value that is adjustable via i 2 c bus. the pup output pin becomes inactive when the voltage at the vsens pin drops below the programmed value of the reference voltage. it is important that the wsen must not be activated before the pup is generated. the pup signal thresh- olds are listed in table 3C8. the internal voltage moni- tor will be activated with a high level at pin dcen. 2.6.2. dc/dc converter the dc/dc converter of the mas 3507d is used to generate a fixed power supply voltage even if the chip set is powered by battery cells in portable applications. the dc/dc converter is designed for the application of 1 or 2 batteries or nicd cells as shown in fig. 2C3 which shows the standard application circuit. the dc/ dc converter is switched on by activating the dcen pin. its output power is sufficient for other ics as well. note : connecting dcen directly to vdd leads to unexpected states of the dccf register. the pup signal should be read out by the system con- troller. a 22 m h inductor is required for the application. the important specification item is the inductor saturation current rating, which should be greater than 2.5 times the dc load current. the dc resistance of the inductor is important for efficiency. the primary criterion for selecting the output filter capacitor is low equivalent series resistance (esr), as the product of the inductor current variation and the esr determines the high-fre- quency amplitude seen on the output voltage. the schottky diode should have a low voltage drop v d for a high overall efficiency of the dc/dc converter. the current rating of the diode should also be greater than 2.5 times the dc output current. the vsens pin has to be always connected to the output voltage. 2.6.3. stand-by functions the digital part of the mas 3507d and the dc/dc converter are turned on by setting wsen. if only the dc/dc converter should work, it can remain active by setting dcen alone to supply other parts of the appli- cation even if the audio decoding part of the mas 3507d is not being used. the wsen power-up pin of the digital part may be handled by the controller. please pay attention to the fact, that i 2 c protocol is working only if the processor and its interfaces works (wsen = 1) table 2C2: clko frequencies f s /khz clko/mhz scaler on clko/mhz scaler off 48, 32 24.576 24.576 44.1 22.5792 22.5792 24, 16 12.288 24.576 22.05 11.2896 22.5792 12, 8 6.144 24.576 11.025 5.6448 22.5792
mas 3507d preliminary data sheet 10 micronas 2.6.4. start-up sequence the dc/dc converter starts from a minimum input voltage of 0.9 v. there should be no output load during startup. in case wsen is active, the mas 3507d is in the dsp operation mode. the start-up script should be as follows: 1. enable the dc/dc-converter with a high signal (vdd, avdd) at pin dcen. 2. wait until pup goes high. 3. wait one more millisecond to guarantee that the out- put voltage has settled (recommended). 4. enable the mas 3507d with a high signal at pin wsen. please also refer to figure 2C2. fig. 2C2: dc/dc operation fig. 2C3: dc/dc converter connections > 0.9 v wsen > 2 v dcen =1 dsp operation controller dc/dc on button voltage monitor dc/dc converter start-up oscillator frequency divider optional filter x2 +32 0...15 32...47 64...94 10 16 - + - + vss avss avdd vdd clki dcso dcsg dcen pup wsen vsense v in 3 0.9 v 22 m h c out 330 m f low esr c in 330 m f dccf $8e 9 47 k w controller 47 k w power-on push button 10 k w 10 nf
preliminary data sheet mas 3507d micronas 11 2.7. interfaces the mas 3507d uses an i 2 c control interface, 2 selectable serial input interfaces for mpeg bit stream (sdi, sdi*) , a parallel i/o interface (pio) for mpeg- or adpcm-data and a digital audio output interface (sdo) for the decoded audio data (i 2 s or similar). additionally, the parallel i/o interface (pio) may be used for monitoring and mode selection tasks. the pio lines are defined by the internal firmware. 2.7.1. mpeg bit stream interface (sdi) the mpeg bit stream input interface uses the three pins: sic, sii , and sid. for mpeg decoding operation, the sii pin must always be connected to vss. the serial interface has to be initialized before the first use. otherwise no output signal is produced. after power-up or a rising slope on pin porq, write the following i 2 c-command, while sic is hold low: w $3a 68 93 b0 00 02 (write $0020 into register $3b) w $3a 68 00 01 (execute run 1 command) the mpeg input signal format is shown in fig. 2C4. the data values are latched with the falling edge of the sic signal. the mpeg bit stream generated by an encoder is unformatted. it will be formatted (e.g. 8 bit or 16 bit) by storing on a media (flash-ram, harddisk). the serial data required from the mpeg bit stream interface must be in the same bit order as produced by the encoder. 2.7.2. sdi* selection an alternative serial input (sdi*) is available. the alter- native serial input can be selected by setting register si1m0 at address $4f (see table 2C3). fig. 2C4: schematic timing of the sdi (mpeg) input table 2C3: sdi* selection via register si1m0, $4f (write) value function 0 use sdi lines 2 use pi14...pi16 pins for serial input (named sdi*) sic sii sid v h v l v h v l v h v l data valid latch data at falling edge of clock
mas 3507d preliminary data sheet 12 micronas 2.7.3. parallel input output interface (pio) the parallel interface of the mas 3507d uses the lines pi0...pi4, pi8, pi12...pi19, and several control lines. 2.7.3.1. pio-dma input mode by setting the pio pin pi4 to 1, the pio-dma input mode of the mas 3507d is activated after reset. normally, the input mode should not be altered in a customers application. should this nonetheless be desired, the necessary changes are described in table 2C4 and table 2C5. 2.7.3.2. writing mpeg data to the pio-dma the pio-dma mode enables the writing of 8-bit paral- lel mpeg data to the mas 3507d. in this mode, pio lines pi19...pi12 are switched to the mas 3507d data input which hence will be an 8-bit parallel input port with msb first (at position pi19) for the mpeg bit stream data. in order to write data to this parallel port successfully, a special handshake protocol has to be used by the controller (see fig. 2C5). note: either sii has to be set to 1, or sic clock input has to be stopped (0) in this mode. . . fig. 2C5: handshake protocol for writing mpeg data to the pio-dma table 2C4: switching from sdi- to pio-dma-input address 1) value $e6, bit 4 1 1) startup configuration register table 2C5: switching from pio-dma- to sdi-input step address 1) value 1 $e6, bit 4 0 2 $4b $82 1) pio configuration register note: these 2 steps must be done in above order! eod pr rtr pi[19:12] high low high low high low high low t st t rpr t rtrq t set t h t r t pr t pd t eodq t eod byte 15 byte 1 mas 3507d latches the pio data
preliminary data sheet mas 3507d micronas 13 2.7.3.3. dma handshake protocol the data transfer can be started after the eod pin of the mas 3507d is set to high. after verifying this, the controller signalizes the sending of data by activating the pr line. the mas 3507d responds by setting the rtr line to the low level. the mas 3507d reads the data pi[19:12] t pd ns after rising edge of the pr . the next data word write operation will again be initialized by setting the pr line via the controller. please refer to figure 2C5 and table 2C6 for the exact timing 2.7.3.4. end of dma transfer the above procedure will be repeated until the mas 3507d sets the eod signal to 0, which indi- cates that the transfer of one data block has been exe- cuted. subsequently, the controller should set pr to 0, wait until eod rises again, and then repeat the procedure (see section 2.7.3.3. ) to send the next block of data. the dma buffer is 15 bytes long. the recommended pio-dma conditions and the char- acteristics of the pio timing are given in table 2C6 2.7.4. audio output interface (sdo) the audio output interface of the mas 3507d is a standard i 2 s interface. it is possible to choose between two standard interfaces (16 bit with delay or 32 bit with- out delay and inverted soi) via start-up configuration. these setup modes meet the performance of the most common dacs. it is also possible to select other inter- face modes via i 2 c commands (see section 2.7.4.3.). 2.7.4.1. mode 1: 16 bits/sample (i 2 s compatible data format) a schematic timing diagram of the sdo interface in 16 bit/sample mode is shown in fig. 2C6. . fig. 2C6: schematic timing of the sdo interface in 16 bit/sample mode table 2C6: pio dma timing symbol pio pin min. max. unit t st pr, eod 0.010 2000 m s t r pr, rtr 40 160 ns t pd pr, pi[19:12] 120 480 ns t set pi[19:12] 160 no limit ns t h pi[19:12] 160 no limit ns t rtrq rtr 200 30000 ns t pr pr 120 no limit ns t rpr pr, rtr 40 no limit ns t eod pr, eod 40 160 ns t eodq eod 0500 m s soc sod v h v l soi left 16-bit audio sample right 16-bit audio sample 15141312111098 76543210 13 12 11 10 9 8 76543210 15 14 v h v l v h v l
mas 3507d preliminary data sheet 14 micronas 2.7.4.2. mode 2:32 bit/sample (inverted soi) if the serial output generates 32 bits per audio sample, only the first 20 bits will carry valid audio data. the 12 trailing bits are set to zero by default (see fig. 2C7) the 12 trailing bits for left and right channel of the sdo interface can be accessed by writing to registers as shown in table 2C7. 2.7.4.3. other output modes the interface is also configurable by software to work in different modes. it is possible to choose: C 16 or 32 bit/sample modes, C inverted or noninverted word strobe (soi), C no delay or delay of data related to word strobe C inverted or noninverted i 2 s-clock (soc). for further details see section 3.7.2.2. fig. 2C7: schematic timing of the sdo interface in 32 bit/sample mode table 2C7: access for trailing bits register bit 0 ... 11 $c5 left channel $c6 right channel 302928272625...76543210 31302928272625 76543210 left 32-bit audio sample right 32-bit audio sample soc sod soi v h v l v h v l v h v l ... ... 31 ...
preliminary data sheet mas 3507d micronas 15 2.8. start-up configuration basic operation of the mas 3507d is possible without controller interaction. configuration and the most important status information are available by the pio interface. the start-up configuration is selected according to the levels of several pio pins. the levels should be set via high impedance resistors (for exam- ple 10 k w) to vss or vdd and will be copied into the startupconfig register directly after power up / reset. after start-up, the pio will be reconfigured as output. to enable greater flexibility, it is possible to configure the mas 3507d without using the pio pins or to recon- figure the ic after start-up. the procedure for this is to send two i 2 c commands to the mas 3507d: C writing the startupconfig register (see section 3.6. on page 26) C execute a run $0fcd command (see section 3.3.1.). the configuration will be active up to a reset. then, the new configuration will be loaded again via pio. 2.8.1. parallel input output interface (pio) during start-up, the pio will read the start-up configu- ration. this is to define the environment for the mas 3507d. the following pins must be connected via resistors to vss or vdd: table 2C8: start-up configuration 1) 1) start-up setting can be changed by i 2 c commands after reset. pio pin 0 1 pi8 divide clko by 1, 2, or 4 (according to mpeg 1, 2, or 2.5) clko fixed at 24.576 or 22.5792 mhz pi4 sdi input mode pio-dma input mode pi3 enable layer 3 disable layer 3 pi2 enable layer 2 disable layer 2 pi1 sdo output: 32 bit sdo output: 16 bit pi0 input: multimedia mode (pll off) input: broadcast mode (pll on)
mas 3507d preliminary data sheet 16 micronas 2.9. status pins in sdi input mode after having read the start-up configuration, the pio will be switched to m p-mode. in m p-mode, the addi- tional pio control lines (pr, pcs ) are evaluated. if the mpeg decoder firmware detects pr = 1 and the pcs = 0. then, all pio interface lines are configured as output and display some status information of the mpeg decoder. the pio lines can be read by an external controller or directly used by dedicated hard- ware blocks (e.g. for sample rate indication or display units). the internal mpeg decoder firmware attaches specific functions to the following pins. the mpeg-frame-sync signal is set to 1 after the internal decoding for the mpeg header has been fin- ished for one frame. the rising edge of this signal could be used as an interrupt input for the controller that triggers the read out of the control information and ancillary data. as soon as the mas 3507d has recog- nized the corresponding read command (read control interface data (see section 3.3.2. on page 21), the mpeg-frame-sync is reset. this behavior reduces the possibility of missing the mpeg-frame-sync active state. fig. 2C8: schematic timing of mpeg-frame-sync the time t read depends on the response time of the controller. this time must not exceed 1/2 of the mpeg- frame length t frame . the mpeg frame lengths are given in table 2C10 . v h l t read mpeg-frame-sync t frame =24 ... 72 ms table 2C9: pio output signals during mpeg decoding in sdi mode pio pin name comment pi19 demand pin %0 %1 no input data exp. input data request pi18, pi17 mpeg index %00 %01 %10 %11 mpeg 2.5 reserved mpeg 2 mpeg 1 pi13, pi12 mpeg layer id %00 %01 %10 %11 reserved layer 3 layer 2 layer 1 1) pi8 mpeg crc-error %0 %1 no error crc-error, mpeg decoding not successful pi4 mpeg-frame- sync see following text pi3, pi2 sampling frequency %00 %01 %10 %11 in khz 2) 44.1 / 22.1 / 11.0 48 / 24 / 12 32 / 16 / 8 reserved pi1, pi0 deemphasis %00 %01 %10 %11 none 50/15 m s reserved ccitt j.17 1) layer 1 bit streams will not be decoded 2) sampling frequency also defined by mpeg index (see table 3C12 for additional information)
preliminary data sheet mas 3507d micronas 17 table 2C10: frame length in mpeg layer 2 / 3 f s in khz frame length layer 2 frame length layer 3 48 24 ms 24 ms 44.1 26.12 ms 26.12 ms 32 36 ms 36 ms 24 24 ms 24 ms 22.05 26.12 ms 26.12 ms 16 32 ms 32 ms 12 not available 48 ms 11.025 not available 52.24 ms 8 not available 72 ms
mas 3507d preliminary data sheet 18 micronas 3. control interfaces 3.1. i 2 c bus interface 3.1.1. device and subaddresses the mas 3507d is controlled via the i 2 c bus slave interface. the ic is selected by transmitting the mas 3507d device addresses. (see table 3C1). writing is done by sending the device write address, ( $3a ) followed by the subaddress byte ( $68 ), two or more bytes of data. reading is done by sending the write device address ($3a), followed by the subad- dress byte ($69). without sending a stop condition, reading of the addressed data is completed by sending the device read address ($3b) and reading n-bytes of data. by means of the reset bit in the control register, the mas 3507d can be reset by the controller. due to the internal architecture of the mas 3507d, the ic cannot react immediately to an i 2 c request. the typical response time is about 0.5 ms. if the mas 3507d cannot accept another complete byte of data until it has performed some other function (for example, decoding mp3 data), it will hold the clock line i2c_cl low to force the transmitter into a wait state. the positions within a transmission where this may happen are indicated by wait in section 3.4. the max- imum wait period of the mas 3507d during normal operation mode is less than 4 ms. table 3C1: i 2 c bus device addresses mas 3507d device address write read mas_i2c_adr $3a $3b table 3C2: i 2 c bus subaddresses name binary value hex value mode function control_mas 0000 0000 $6a write control subaddress (see table 3C3) wr_mas 0110 1000 $68 write write subaddress rd_mas 0110 1001 $69 write read subaddress table 3C3: control register (subaddress: $6a) name subaddress bit : 8 bit : 0-7, 9-15 control $6a 1 : reset 0 : normal 0
preliminary data sheet mas 3507d micronas 19 note: s = i 2 c-bus start condition from master p = i 2 c-bus stop condition from master ack = acknowledge-bit: low on i2c_da from slave or master nak = not acknowledge-bit: high on i2c_da from master to indicate end of read wait = i 2 c-clock line is held low, while the mas 3507d is processing the i 2 c command. fig. 3C1: i 2 c bus protocol (msb first; data must be stable while clock is high) 3.2. command structure the i 2 c control of the mas 3507d is done completely via the i 2 c data register by using a special command syntax. the commands are executed by the mas 3507d during its normal operation without any loss or interruption of the incoming data or outgoing audio data stream. these i 2 c commands allow the controller to access internal states, ram contents, internal hardware control registers, and even a down- load of an alternative software module. the command structure allows sophisticated control of the mas 3507d. the registers of the mas 3507d are either general purpose, e.g. for program flow control, or specialized registers that directly affect hardware blocks. the unrestricted access to these registers allows the system controller to overrule the firmware configuration of the serial interfaces or the default input line selection. the control interface is also used for low bit rate data transmission, e.g. mpeg-embedded ancillary data transmission. the data information is performed by sending a read memory command to the mas 3507d and by reading the memory block that temporarily con- tains the required information. the synchronization between the controller and the mas 3507d is done via a mpeg-frame-sync signal or by monitoring the mpegframecount register (at the cost of a higher work load for the controller). the mas 3507d firmware scans the i 2 c interface peri- odically and checks for pending or new commands. however, due to some time critical firmware parts, a certain latency time for the response has to be expected. the theoretical worst case response time does not exceed 4 ms. table 3C4 shows the basic con- troller commands that are available by the mas 3507d. 3.2.1. the internal fixed point number format internal register or memory values can easily be accessed via the i 2 c interface. in this document, two number representations are used: the fixed point nota- tion v and the 2s complement number notation r. the conversion between the two forms of notation is easily done (see the following equations). r = v x 524288.0 + 0.5; ( - 1.0 v < 1.0) (eq 1) v = r / 524288.0; ( - 524288 < r < 524287) (eq 2) 1 0 s p i2c_da i2c_cl
mas 3507d preliminary data sheet 20 micronas 3.2.2. conventions for the command description the description of the various controller commands uses the following formalism: C a data value is split into 4-bit nibbles which are num- bered beginning with 0 for the least significant nib- ble. C data values in nibbles are always shown in hexa- decimal notation indicated by a preceding $. C a hexadecimal 20-bit number d is written, e.g. as d = $17c63, its five nibbles are d0 = $3, d1 = $6, d2 = $c, d3 = $7, and d4 = $1. C abbreviations used in the following descriptions: a address d data value n count value o offset value r register number x dont care C variables used in the following descriptions: dev_write $3a dev_read $3b data_write $68 data_read $69 control $6a 3.3. detailed mas 3507d command syntax 3.3.1. run the run command causes the start of a program part at address a = (a3,a2,a1,a0). the nibble a3 is restricted to $0 or $1 which also acts as command selector. run with address a=$0 will suspend normal mpeg decoding and only i 2 c commands are evalu- ated. this freezing will be required if alternative soft- ware is downloaded into the internal ram of the mas 3507d. detailed information about downloading is provided in combination with a mas 3507d software development package or together with mas 3507d software modules available from micronas. if the address $1400 a < $1800, the mas 3507d continues execution of the program with the down- loaded code. for detailed information, please refer to the masc software development kit. this is for starting the downloaded program code. example 1: run at address $fcd (override start-up configuration) has the following i 2 c protocol: <$3a><$68><$0f><$cd> example 2: run at address $475 (activate plloffset and outputconfig after change by write command) has the following i 2 c protocol: <$3a><$68><$04><$75> s dev_write a data_write a a3 , a2 a p a1,a0 a table 3C4: basic controller commands code command comment $0 $1 run start execution of an internal program. (run 0 means freeze operating sys- tem.) $3 read control informa- tion and ancillary data fast read of a block of information organized in 16-bit words (see section 3.7.1. on page 30) $9 write register an internal register of the mas 3507d can be written directly to by the con- troller. $a $b write to memory a block of the dsp memory can be written to by the controller. this feature may be used to download alternate programs. $d read register the controller can read an internal register of the mas 3507d. $e $f read memory a block of the dsp memory can be read by the controller.
preliminary data sheet mas 3507d micronas 21 3.3.2. read control interface data an internal memory array keeps the status information of the mas 3507d (see table 3C10). the read control interface data command can be used for quick access to this memory array. a successive range of memory locations may be read by passing a 6-bit offset value o and a 6-bit count value n as parameter. both values are combined in a 12-bit = 4 nibble field x2, x1, x0. if, for example, 4 words (n = 4) starting with one word offset (o = 2), i.e. the mpeg status 2, the crcerrorcount, and numberofancillarybits are read from the control memory array, the 3 nibbles x2, x1 and x0 are evaluated as shown in the following table. the complete i 2 c protocol reads as: <$3a><$68><$30><$83> <$3a><$69><$3b> the read control interface data command resets the mpeg-frame-sync at pi4 pin (see section 2.9. on page 16). 3.3.3. write register the controller writes the 20-bit value ( d = d4,d3,d2,d1,d0) into the mas 3507d register ( r = r1,r0). in contrast to memory cells, registers are always addressed individually, and they may also inter- act with built-in hardware blocks. a list of useful regis- ters is given in the next section. example: muting can be realized by writing the value 1 into the register with the number $aa: <$3a><$68><$9a><$a1><$00><$00> 3.3.4. write d0 memory the mas 3507d has 2 memory areas of 2048 words each called d0 and d1 memory. for both memory areas, read and write commands are provided. example: reconfiguration of the output to 16 bit without delay has the following i 2 c protocol: <$3a><$68><$a0><$00> (write d0 memory) <$00><$01> (1 word to write) <$03><$2f> (start address) <$00><$10> (value = $00010) <$00><$00> <$3a><$68><$04><$75> (run command) 3.3.5. write d1 memory for further details, see write d0 memory command. 11 10 9 8 7 6 5 4 3 2 1 0 6-bit values offset: 2 number of words: 3 bit 000010000011 nibble 0 8 3 s dev_write a data_write a $3 , x2 a d3, d2 x1,x0 s dev_write a data_read a s dev_read a a d1,d0 a nak p 1) send command 2) get ancillary data values ....repeat for n data values.... d3, d2 a d1,d0 d3...d0: 16-bit data values (ancillary word 0) a p x2...x0: combined count, offset value s s dev_write a data_write a $9 , r1 a p r0, d0 a d4, d3 a d2, d1 a s dev_write a data_write $a , $0 a $0,$0 a n3,n2 a n1,n0 a a3,a2 a1,a0 n3..n0: number of words a3..a0: start address in masd memory d4..d0: data value a n3,n2 a n3,n2 a d1,d0 a $0,$0 $0,d4 a d3,d2 ....repeat for n data values.... a n3,n2 a d1,d0 a $0,$0 $0,d4 a d3,d2 a p a s dev_write a data_write a $b , $0 a $0,$0 a n3,n2 a n1,n0 a a3,a2 a1,a0 n3..n0: number of words to be transmitted a3..a0: start address in masd memory d4..d0: data value a n3,n2 a n3,n2 a d1,d0 a $0,$0 $0,d4 a d3,d2 ....repeat for n data values.... a n3,n2 a d1,d0 a $0,$0 $0,d4 a d3,d2 a p
mas 3507d preliminary data sheet 22 micronas 3.3.6. read register the mas 3507d has an address space of 256 regis- ters. some of the registers ( r = r1,r0 in the figure above) are direct control inputs for various hardware blocks, others do control the internal program flow. in the next section, those registers that are of any interest with respect to the mpeg decoding are described in detail. example: read the content of the pio data register ($c8): <$3a><$68><$dc><$80> <$3a><$69><$3b> now read: 3.3.7. read d0 memory the read d0 memory command is provided to get information from memory cells of the mas 3507d. it gives the controller access to all memory cells of the internal d0 memory. direct access to memory cells is an advanced feature of the dsp. it is intended for users of the masc software development kit. 3.3.8. read d1 memory the read d1 memory command is provided to get information from memory cells of the mas 3507d. it gives the controller access to all memory cells of the internal d1 memory. 3.3.9. default read the default read command immediately returns the content of the mpegframecount (d0:$300) of the mas 3507d in the variable ( d = d3,d2,d1,d0). the default read command is the fastest way to get infor- mation from the mas 3507d. executing the default read command in a polling loop can be used to detect the availability of new ancillary data. s dev_write a data_write a $d , r1 a d3, d2 p r0,$0 a s dev_write a data_read a s dev_read a a d1,d0 a x,x a x, d4 nak p 1) send command 2) get register value r1, r0: register r d3...d0: data value in r x: dont care s dev_write a data_write a $e , $0 a d3, d2 $0,$0 a s dev_write a data_read a s dev_read a a d1,d0 a $0,$0 a $0, d4 1) send command 2) get memory value n3,n2 n1,n0 a a3,a2 a a1,a0 a ....repeat for n data values.... n3..n0: number of words a3..a0: start address in masd memory d4..d0: data value a d3, d2 a d1,d0 a $0,$0 a $0, d4 p nak p a s dev_write a data_write a $f , $0 a d3, d2 $0,$0 a s dev_write a data_read a s dev_read a a d1,d0 a $0,$0 a $0, d4 1) send command 2) get memory value n3,n2 n1,n0 a a3,a2 a p a1,a0 a a ....repeat for n data values.... n3..n0: number of words a3..a0: start address in masd memory d4..d0: data value a d3, d2 a d1,d0 a $0,$0 a $0, d4 p nak s dev_write a data_read a s device_read a d3,d2 nak p a d1,d0
preliminary data sheet mas 3507d micronas 23 3.4. protocol description 3.4.1. run command 3.4.2. read control interface data send command get ancillary data values 3.4.3. write to mas 3507d register 3.4.4. write to mas 3507d d0 memory s $3a ack $68 ack a3, a2 ack a1, a0 wait ack p s $3a ack $68 ack $3, x2 ack x1, x0 wait ack p s $3a ack $69 ack s $3b wait ack d3, d2 ack d1, d0 wait .... repeat for n data values ack d3, d2 ack d1, d0 wait nak p s $3a ack $68 ack $9,r1 ack r0,d0 wait ack d4,d3 ack d2,d1 wait ack p s $3a ack $68 ack $a, $0 ack $0, $0 wait ack n3, n2 ack n1, n0 wait ack a3, a2 ack a1, a0 wait ack d3, d2 ack d1, d0 wait ack $0, $0 ack $0, $d4 wait .... repeat for n data values ack d3, d2 ack d1, d0 wait ack $0, $0 ack $0, $d4 wait ack p
mas 3507d preliminary data sheet 24 micronas 3.4.5. write to mas 3507d d1 memory 3.4.6. read register send command get register value 3.4.7. read d0 memory send command get memory values 3.4.8. read d1 memory send command s $3a ack $68 ack $b, $0 ack $0, $0 wait ack n3, n2 ack n1, n0 wait ack a3, a2 ack a1, a0 wait ack d3, d2 ack d1, d0 wait ack $0, $0 ack $0, $d4 wait .... repeat for n data values ack d3, d2 ack d1, d0 wait ack $0, $0 ack $0, $d4 wait ack p s $3a ack $68 ack $d, r1 ack r0, $0 wait ack p s $3a ack $69 ack s $3b wait ack d3, d2 ack d1, d0 wait ack x, x ack x, d4 wait nak p s $3a ack $68 ack $e, $0 ack $0, $0 wait ack n3, n2 ack n1, n0 wait ack a3, a2 ack a1, a0 wait ack p s $3a ack $69 ack s $3b wait ack d3, d2 ack d1, d0 wait ack $0, $0 ack $0, d4 wait .... repeat for n data values ack d3, d2 ack d1, d0 wait ack d3, d2 ack d1, d0 wait nak p s $3a ack $68 ack $f, $0 ack $0, $0 wait ack n3, n2 ack n1, n0 wait ack a3, a2 ack a1, a0 wait ack p
preliminary data sheet mas 3507d micronas 25 get memory values 3.4.9. default read 3.4.10.write data to the control register 3.5. version number table 3C5 shows where the mas 3507d hardware ver- sion, its software and additional information is located. s $3a ack $69 ack s $3b wait ack d3, d2 ack d1, d0 wait ack $0, $0 ack $0, d4 wait .... repeat for n data values ack d3, d2 ack d1, d0 wait ack d3, d2 ack d1, d0 wait nak p s $3a ack $69 ack s $3b wait ack d3, d2 ack d1, d0 wait nak p s $3a ack $6a ack d3, d2 ack d1, d0 wait ack p table 3C5: mas 3507d version addr. content example value d1:$ff6 name of mas 3507d ver- sion 0x03507 3507 d1:$ff7 hardware/software design code mas 3507d f10 0x00601 (increases for new versions) 0601 d1:$ff9 description: mpeg 1/2.5 l23 0x04d50 mp d1:$ffa 0x04547 eg d1:$ffb 0x02031 1 d1:$ffc 0x02f32 /2 d1:$ffd 0x02e35 .5 d1:$ffe 0x0204c l d1:$fff 0x03233 23
mas 3507d preliminary data sheet 26 micronas 3.6. register table in table 3C6, the internal registers that are useful for controlling the mas 3507d are listed. they are acces- sible by register read/write i 2 c commands (see sec- tion 3.3. on page 20). important note! writing into undocumented registers or read-only registers is always possible, but it is highly recommended not to do so. it may damage the func- tion of the firmware and may even lead to a complete system crash of the decoder operation which can only be restored by a reset. 3.6.1. dc/dc converter the dccf register controls both the internal voltage monitor and dc/dc converter. between output voltage of the dc/dc converter and the internal voltage moni- tor threshold an offset exists which is shown in the fol- lowing table. please pay attention to the fact, that i 2 c protocol is working only if the processor is active (wsen = 1). however, the setting for the dccf regis- ter will remain active if the dcen and wsen lines are deasserted table 3C6: command register table address r/w name comment default $8e w dccf set dc/dc converter mode (see table 3C7 on page 27) $08000 $aa r/w mute / bypass tone control forces a mute of the digital output bypass bass / treble / volume matrix $0 $ed 1) r piodata read back the pio pin levels. the pi0 pin corresponds to bit 0 in the piodata register. this register can be used to detect the actual state of the pio pins, regardless of the pio configuration. $e6 r/w startupconfig shadows the start-up configuration set via pio pins or i 2 c command (valid are bits 8, 4...0 as described in table 2C8. $e7 r/w kprescale responsible for prescale of the tone filter (prevent overflows) (see section 3.6.3. on page 28) $80000 $6b r/w kbass responsible for increase / decrease of low frequencies (see section 3.6.3. on page 28) $0 $6f r/w ktreble responsible for increase / decrease of high frequencies (see section 3.6.3. on page 28) $0 1) in order to get the right information of the pio pin levels (except for pi19, demand pin), register $ed should be read and evaluated. however, the demand pin pi19 is shadowed in bit 19 of register $c8.
preliminary data sheet mas 3507d micronas 27 the dc/dc converter may generate interference noise that could be unacceptable for some applications. thus the oscillator frequency may be adjusted in 16 steps in order to allow the system controller to select a base frequency that does not interfere with an other application. the clki input provides the base clock f ckli for the frequency divider whose output is made symmetrical with an additional divider by two. the divider quotient is determined by the content of the dccf register. this register allows 32 settings generating a dc/dc converter clock frequency f dc between: (eq 3) table 3C7: dc/dc-converter switch frequency (bits 8, 13..10 of dccf-register) dccf value (hex) 1) f sw bit 8 = 0 bit 8 = 1 0cc00 0c800 0c400 0c000 04c00 04800 04400 04000 01c00 01800 01400 01000 00c00 00800 00400 00000 156 khz 160 khz 163 khz 167 khz 171 khz 175 khz 179 khz 184 khz 188 khz 194 khz 199 khz 204 khz 210 khz 216 khz 223 khz 230 khz 238 khz 245 khz 253 khz 263 khz 272 khz 283 khz 295 khz 307 khz 320 khz 335 khz 351 khz 368 khz 387 khz 409 khz 433 khz 460 khz 1) all other bits are set to zero (dc/dc-converter output voltage = 3.0 v) f sw f ckli 2 m n + () ------------------------- = n 015 {, } ? m 16 32 , {} ? , table 3C8: dc converter output voltages (bits 16..14, bit 9 of dccf-register) dccf value (hex) 1) dc/dc converter output internal voltage monitor 2) 1c000 18000 14000 10000 0c000 08000 04000 00000 1c200 18200 14200 10200 0c200 08200 04200 00200 3.5 v 3.4 v 3.3 v 3.2 v 3.1 v 3.0 v 2.9 v 2,8 v 2.7 v 2.6 v 2.5 v 2.4 v 2.3 v 2.2 v 2.1 v 2.0 v 3.3 v 3.2 v 3.1 v 3.0 v 2.9 v 2,8 v 2.7 v 2.6 v 2.5 v 2.4 v 2.3 v 2.2 v 2.1 v 2.0 v 1.9 v 1.8 v 1) all other bits are set to zero (f sw = 230 khz) 2) pup signal becomes inactive when output below
mas 3507d preliminary data sheet 28 micronas 3.6.2. muting / bypass tone control to enable fast and simple mute functionality, set bit 0 in register $aa to 1. writing a 0 deactivates mute. it is possible to bypass the complete bass / treble / volume control by setting bit 1 in register $aa (write a 2). reset- ting bit 1 to 0 enables tone control again. 3.6.3. bass and treble control tone control is implemented in the mas 3507d. it allows the control of bass and treble in a range up to 15 db, as table 3C9 shows. to prevent overflow or clipping effects, the prescaler is built-in. the prescaler decreases the overall gain of the tone filter, so the full range up to +15 db is usable without clipping. to select a special setting, max. 3 coefficients have to be written into registers of the mas 3507d. this has to be done via the write register i 2 c command (see section 3.3.3.). address r/w name comment default $aa r/w mute / bypass tone control 0 1 2 forces a mute of the digital output no mute, tone control active mute output, but continue decoding bypass bass / treble / volume matrix $0 address r/w name comment default $e7 r/w kprescale responsible for prescale of the tone filter (prevent overflows) (see section 2.4.3. on page 8) $80000 $6b r/w kbass responsible for increase / decrease of low frequencies (see section 2.4.3. on page 8) $0 $6f r/w ktreble responsible for increase / decrease of high frequencies (see section 2.4.3. on page 8) $0
preliminary data sheet mas 3507d micronas 29 table 3C9: tone control registers boost in db bass (reg. $6b) treble (reg. $6f) prefactor (reg $e7) +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 $61800 $5d400 $58800 $53800 $4e400 $48800 $42800 $3c000 $35800 $2e400 $27000 $1f800 $17c00 $10000 $800 $5f800 $58400 $51800 $49c00 $42c00 $3c000 $35400 $2ec00 $28400 $22000 $1c000 $16000 $10400 $ac00 $5400 $e9400 $e6800 $e3400 $dfc00 $dc000 $d7800 $d25c0 $cd000 $c6c00 $bfc00 $b8000 $af400 $a5800 $9a400 $8e000 0 0 0 $80000 - 1 - 2 - 3 - 4 - 5 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 $f7c00 $efc00 $e8000 $e0400 $d8c00 $d1800 $ca400 $c3c00 $bd400 $b7400 $b1800 $ac400 $a7400 $a2800 $9e400 $fac00 $f5c00 $f0c00 $ec000 $e7e00 $e2800 $de000 $d9800 $d5000 $d0400 $cbc00 $c6c00 $c1800 $bb400 $b2c00 $80000 $80000 $80000 $80000 $80000 $80000 $80000 $80000 $80000 $80000 $80000 $80000 $80000 $80000 $80000
mas 3507d preliminary data sheet 30 micronas 3.7. memory area 3.7.1. status memory the memory cells given in the following table should be accessed by the read control interface data i 2 c command (see section 3.3.2. on page 21) because only the 16 lsbs of these memory blocks are used. the memory area table is a consecutive memory block in the d0 memory that keeps all important status information that monitors the mpeg decoding process. the read control interface data command resets the mpeg-frame-sync at pi4 as described in section 2.9. 3.7.1.1. mpeg frame counter the counter will be incremented with each new frame that is decoded. with an invalid mpeg bit stream as its input (e.g. if an invalid header is detected), the mas 3507d resets the mpegframecount cell to 0. the mpegframe- count is also returned by the default read command as described in section 3.3.9. table 3C10: status memory area address offset 1) r/w name function d0:$300 0 r mpegframecount counts the mpeg frames d0:$301 1 r mpegstatus1 mpeg header / status information d0:$302 2 r mpegstatus2 mpeg header d0:$303 3 r crcerrorcount counts crc errors during mpeg decoding d0:$304 4 r numberofancillarybits number of bits in ancillary data d0:$305 ... $321 5 r ancillarydata organized in words a 16 bit (msb first) 1) offset applies to the read control interface data command address offset r/w name function d0:$300 0 r mpegframecount counts the mpeg frames
preliminary data sheet mas 3507d micronas 31 3.7.1.2. mpeg status 1 the mpeg status 1 contains the bits 15...11 of the mpeg header and some status bits. it will be set each frame, directly after the header has been decoded from the bit stream. address offset r/w name function d0:$301 1 r mpegstatus 1 mpeg header / status information table 3C11: mpeg status 1 bits name/value comment 19, 15 %xxxx.x dont care 14, 13 mpeg id %00 %01 %10 %11 bits 11, 12 of the mpeg-header mpeg 2.5 reserved mpeg 2 mpeg 1 12, 11 layer %00 %01 %10 %11 bits 13, 14 of the mpeg-header reserved layer 3 layer 2 layer 1 (not supported) 10 %1 not protected by crc 9...2 private bits 1 %1 crc error 0 %1 invalid frame
mas 3507d preliminary data sheet 32 micronas 3.7.1.3. mpeg status 2 the mpeg status 2 contains the 16 lsbs of the mpeg header. it will be set directly after synchronizing to the bit stream. address offset r/w name function d0:$302 2 r mpeg status 2 mpeg header table 3C12: mpeg status 2 bits value/name comment 19, 16 dont care 15...12 bit rate index mpeg 1 (layer 2) in kbit/s mpeg 1 (layer 3) in kbit/s mpeg 2 in kbit/s (layer 2 & 3) mpeg 2.5 in kbit/s %0000 %0001 %0010 %0011 %0100 %0101 %0110 %0111 %1000 %1001 %1010 %1011 %1100 %1101 %1110 %1111 free 32 48 56 64 80 96 112 128 160 192 224 256 320 384 forbidden free 32 40 48 56 64 80 96 112 128 160 192 224 256 320 forbidden free 8 16 24 32 40 48 56 64 80 96 112 128 144 160 forbidden 11, 10 sampling frequency mpeg 1 mpeg 2 mpeg 2.5 %00 %01 %10 %11 44.1 khz 48 khz 32 khz reserved 22.05 khz 24 khz 16 khz reserved 11.025 khz 12 khz 8khz reserved 9 padding bit 8 private bit 7, 6 mode %00 %01 %10 %11 stereo joint_stereo (intensity stereo / ms_stereo) dual channel single_channel 5, 4 mode extension (if joint stereo only) intensity stereo ms_stereo %00 %01 %10 %11 off on off on off off on on 3 %0 / 1 copyright not protected / copyright protected
preliminary data sheet mas 3507d micronas 33 3.7.1.4. crc error counter the counter will be increased by each crc error in the mpeg bit stream. it will not be reset by losing the synchroni- zation. 3.7.1.5. number of ancillary bits this cell displays the number of valid ancillary bits stored beginning at d0:$305. 2 %0 / 1 copy / original 1, 0 emphasis indicates the type of emphasis %00 %01 %10 %11 none 50/15 m s reserved ccitt j.17 table 3C12: mpeg status 2 bits value/name comment address offset r/w name function d0:$303 3 r crcerrorcount counts crc errors during mpeg decoding address offset r/w name function d0:$304 4 r numberofancillarybits number of bits in ancillary data
mas 3507d preliminary data sheet 34 micronas 3.7.1.6. ancillary data this memory field contains the ancillary data. it is organized in words 16 bit each. the last ancillary bit transmitted in a frame is placed at bit 0 in d0:$305. the position of the first ancillary data bit is locatable via the content of number- ofancillarybits. an example: 17 bits ancillary data in a frame: a possible read ancillary data algorithm would read the numberofancillarybits and the complete ancillary data area using the telegram: <$3a><$68><$31><$1e> (offset=4, n=30) <$3a><$69><$3b> for reducing the i 2 c protocol transfer traffic, it may be useful to split up the read ancillary data algorithm into a first part that reads numberofancillarybits and a second that reads only numberofancillarybits/16+1 words. address offset r/w name function d0:$305 ... d0:$321 5 r ancillarydata organized in words a 16 bit (msb first) table 3C13: ancillary data bit assignment d0: $305 15 msb 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 lsb ancillary data bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15 bit 16 table 3C14: ancillary data bit assignment d0: $306 15 msb 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 lsb ancillary data x x x x x x x x x x x x x x x bit 0
preliminary data sheet mas 3507d micronas 35 3.7.2. configuration memory the configuration memory allows the controller advanced configuration possibilities, e.g. changing setups for the crystal frequency or changing the digital format of the serial audio output data interface. table 3C15: configuration memory area 1) 1) important note: writing into undocumented memory cells is always possible, but it is highly recommended not to do so. it may damage the function of the firmware and may even lead to a complete system crash of the decoder operation which can only be restored by a reset. address r/w name function default d0:$36d r/w plloffset48 pll offset (if f s = 48, 24, 12, 32, 16, or 8 khz), validate by run $475 command d0:$36e r/w plloffset44 pll offset (if f s = 44.1, 22.05, 11.025 khz), validate by run $475 command d0:$36f r/w outputconfig configuration of the i 2 s audio output interface validate by run $475 command d1:$7f8 r/w ll left ? left gain $80000 d1:$7f9 r/w lr left ? right gain 0 d1:$7fa r/w rl right ? left gain 0 d1:$7fb r/w rr right ? right gain $80000
mas 3507d preliminary data sheet 36 micronas 3.7.2.1. pll offset for 44/48 khz sampling frequency with these memory cells it is possible to choose other frequencies than the standard clki frequencies. please note: C plloffset48 is valid for f s = 48, 24, 12, 32, 16, or 8 khz. C plloffset44 is valid for f s = 44.1, 22.05, 11.025 khz. table 3C16 shows the default values which will be set by the firmware according to the start-up configuration. it is also possible to run the mas 3507d with other clocks. in broadcast mode, it is necessary to adjust the plloffsets to this clock, otherwise it will not lock to the mpeg bit stream. in multimedia mode, it is recom- mended to adjust the plloffsets to the crystal, other- wise it would result in a frequency shift (music will be played faster or slower). for adjusting, the following procedure must be done: C calculate the plloffsets according to: with - 0.74 < plloffset < 0.74. this corresponds to a frequency range of 14.31...14.73 mhz for the crystal, if both 44.1 khz and 48 khz based sample frequencies are used. the range is extended in an application with a fixed sampling frequency, as table 3C17 shows. C write the plloffsets to the memory (plloffset48 d0:$36d, plloffset44 d0:$36e). C send a run $475 command. with the jump to this address, the settings in the memory will be valid for the internal processing. example: a very common crystal frequency is 14.31818 mhz (ntsc color subcarrier). the and are inside the range - 0.74 ... 0.74. address r/w name function default d0:$36d r/w plloffset48 pll offset (if f s = 48, 24, 12, 32, 16, or 8 khz), validate by run $475 command d0:$36e r/w plloffset44 pll offset (if f s = 44.1, 22.05, 11.025 khz), validate by run $475 command table 3C16: plloffset48 and plloffset44 f clki plloffset48 plloffset44 14.725 mhz 0.351986 - 0.732862 f clki 24,576 8 13 plloffset 48 + --------------------------------------------- - 22,5792 8 13 plloffset 44 + --------------------------------------------- - == table 3C17: f clki for max./ min. plloffsets plloffset f clki for f s related to 48 khz fclki for fs related to 44.1 khz - 0.74 16.0365 mhz 14.7336 mhz 0.74 14.309 mhz 13.1465 mhz plloffset 48 24,576 8 14,31818 ----------------------- - 13 C0,7314 == plloffset 44 22,5792 8 14,31818 -------------------------- - 13 C 0,3843 C ==
preliminary data sheet mas 3507d micronas 37 3.7.2.2. output configuration the content of this memory cell depends on the start- up configuration and will be set by the firmware. never- theless, the audio output interface is configurable by the software to work in different 16 bit/sample modes and 32 bit/sample modes (see section 2.7.4. on page 13). for adjusting to this, the following procedure has to be done: C choose the output mode (see table 3C18). C write this value to the memory (d0:$36f). C send a run $475 command. with the jump to this address, the settings in the memory will become valid for the internal processing. this overrides all start-up settings 3.7.3. baseband volume matrix the digital baseband volume matrix is used for con- trolling the digital gain and a simple kind of stereo basewidth enlargement as shown in fig. 3C2. table 3C 20 shows the proposed settings for the 4 volume matrix coefficients for stereo, left and right mono. the gain factors are given in fixed point notation. the gain values may be written to the mas 3507d by the con- troller command write d1 memory. address r/w name function default d0:$36f r/w outputconfig configuration of the i 2 s audio output interface validate by run $475 command address r/w name function default d1:$7f8 r/w ll left->left gain $80000 d1:$7f9 r/w lr left->right gain $0 d1:$7fa r/w rl right->left gain $0 d1:$7fb r/w rr right->right gain $80000 table 3C18: output configuration bits value comment 19...15 %0000.0 dont care 14 %0 %1 soc standard tim- ing soc inverted tim- ing 13..12 %00. dont care 11 %0 %1 no delay additional delay of data related to word strobe 10...6 %000.00 dont care 5%0 %1 not invert invert outgoing word strobe signal 4%0 %1 32 bits/sample 16 bits/sample 3...0 %0000 dont care table 3C19: bit assignment of the volume cells bits name value comment 19..0 ll/lr/rl/rr - 524288/524288..524287/524288 = - 1.0 .. 1.0 - 2^ - 19
mas 3507d preliminary data sheet 38 micronas fig. 3C2: digital volume matrix the fixed point gain values correspond to 20 bit 2s complement notation. the conversion between fixed point and 2s complement notation is done easily by the algorithms described in section 3.2.1. table 3C21 contains the converted gain values as used in the write d1 memory command - 1 - 1 - 1 - 1 ll lr rl rr + + left audio right audio table 3C20: settings for the digital volume matrix memory location d1: $7f8 d1: $7f9 d1: $7fa d1: $7fb name ll lr rl rr stereo (default) - 1.0 0 0 - 1.0 mono left - 1.0 - 1.0 0 0 mono right 00 - 1.0 - 1.0 table 3C21: volume matrix conversion (db into hexadecimal) volume (in db) hexa decimal volume (in db) hexa decimal volume (in db) hexa decimal volume (in db) hexa decimal volume (in db) hexa decimal 0 80000 - 20 f3333 - 40 feb85 - 60 ffdf4 - 80 fffcc - 1 8deb8 - 21 f4979 - 41 fedbf - 61 ffe2d - 81 fffd1 - 29a537 - 22 f5d52 - 42 fefbb - 62 ffe60 - 82 fffd6 - 3 a5621 - 23 f6f03 - 43 ff180 - 63 ffe8d - 83 fffdb - 4af3cd - 24 f7ec8 - 44 ff314 - 64 ffeb5 - 84 fffdf - 5 b8053 - 25 f8cd5 - 45 ff47c - 65 ffed9 - 85 fffe3 - 6bfd92 - 26 f995b - 46 ff5bc - 66 ffef9 - 86 fffe6 - 7 c6d31 - 27 fa485 - 47 ff6da - 67 fff16 - 87 fffe9 - 8 cd0ad - 28 fae78 - 48 ff7d9 - 68 fff2f - 88 fffeb - 9 d2958 - 29 fb756 - 49 ff8bc - 69 fff46 - 89 fffed - 10 d785e - 30 fbf3d - 50 ff986 - 70 fff5a - 90 fffef - 11 dbecc - 31 fc648 - 51 ffa3a - 71 fff6c - 91 ffff1 - 12 dfd91 - 32 fcc8e - 52 ffadb - 72 fff7c - 92 ffff3 - 13 e3583 - 33 fd227 - 53 ffb6a - 73 fff8b - 93 ffff4 - 14 e675f - 34 fd723 - 54 ffbea - 74 fff97 - 94 ffff6 - 15 e93cf - 35 fdb95 - 55 ffc5c - 75 fffa3 - 95 ffff7 - 16 ebb6a - 36 fdf8b - 56 ffcc1 - 76 fffad - 96 ffff8 - 17 edeb6 - 37 fe312 - 57 ffd1b - 77 fffb6 - 97 ffff9 - 18 efe2c - 38 fe638 - 58 ffd6c - 78 fffbe - 98 ffff9 - 19 f1a36 - 39 fe905 - 59 ffdb4 - 79 fffc5 - 99 ffffa
preliminary data sheet mas 3507d micronas 39 4. specifications 4.1. outline dimensions fig. 4C1: 44-pin plastic leaded chip carrier package (plcc44) weight approximately 2.5 g dimensions in mm fig. 4C2: 44-pin plastic quad flat package (pmqfp44) weight approximately 0.4 g dimensions in mm note: start pin and orientation of pin numbering is different for plcc and pmqfp packages! 15.7 0.3 10 x 1.27 = 12.7 0.1 1.2 x 45 140 39 29 28 18 17 7 6 1.6 0.1 5 8.6 5 2 2 x 45 1.1 1.27 1.27 spgs0027-2(p44/k)/1e 17.52 0.12 17.52 0.12 16.5 0.1 16.5 0.1 10 x 1.27 = 12.7 0.1 4.75 0.15 4.05 0.1 1.9 0.05 0.28 0.04 0.71 0.05 0.48 0.06 0.9 0.2 spgs706000-2(p44)/1e 34 44 1 11 12 22 23 33 1.3 1.75 1.75 0.1 0.8 0.8 13.2 0.2 13.2 0.2 0.17 0.06 2.15 0.2 2.0 0.1 0.375 0.075 10 0.1 10 0.1 10 x 0.8 = 8 0.1 10 x 0.8 = 8 0.1
mas 3507d preliminary data sheet 40 micronas fig. 4C3: 49-ball plastic ball grid array (pbga49) weight approximately 0.13 g dimensions in mm 4.2. pin connections and short descriptions nc not connected, leave vacant lv if not used, leave vacant x obligatory, pin must be connected as described in application information vdd connect to positive supply vss connect to ground 0.46 6 x 0.8 = 4.8 spgs0007-1/2e 7 0.8 7 6 x 0.8 = 4.8 0.8 a b c d e f g 1 2 3 4 5 6 7 1.4 0.36 ? 1.04 1.1 1.1 a1 ball pad corner pin no. pin name type connection short description pmqfp 44-pin plcc 44-pin pbga 49-ball test alias in () (if not used) 1 6 c3 te in vss test enable 25c2por in vdd reset, active low 34b1i2cc in/outx i 2 c clock line 43d2i2cd in/outx i 2 c data line 5 2 c1 vdd supply x positive supply for digital parts 6 1 d1 vss supply x ground supply for digital parts 7 44 e2 dcen in vss enable dc/dc converter 843e1eod out lv pio end of dma, active low 942f2rtr out lv pio ready to read, active low 10 41 f1 rtw out lv pio ready to write, active low 11 40 g1 dcsg supply vss dc converter transistor ground 12 39 e3 dcso out vss dc converter transistor open drain 13 38 f3 vsens in vdd dc converter voltage sense 14 37 g2 pr in x pio-dma request or read/write
preliminary data sheet mas 3507d micronas 41 15 36 f4 pcs in x pio chip select, active low 16 35 g3 pi19 in/out lv pio data [19] 1. demand pin in sdi mode 2. data bit [7], msb (pio-dma input mode) 17 34 e4 pi18 in/out lv pio data [18] 1. mpeg header bit 11 - mpeg id (sdi mode) 2. data bit [6] (pio-dma input mode) 18 33 g4 pi17 in/out lv pio data [17] 1. mpeg header bit 12 C mpeg id (sdi mode) 2. data bit [5] (pio-dma input mode) 19 32 f5 pi16 in/out lv pio data [16] 1. sic*, alternative input for sic (sdi mode) 2. data bit [4] (pio-dma input mode) 20 31 g5 pi15 in/out lv pio data [15] 1. sii*, alternative input for sii (sdi mode) 2. data bit [3] (pio-dma input mode) 21 30 f6 pi14 in/out lv pio data [14] 1. sid*, alternative input for sid (sdi mode) 2. data bit [2] (pio-dma input mode) 22 29 g6 pi13 in/out lv pio data [13] 1. mpeg header bit 13 C layer id (sdi mode) 2. data bit [1] (pio-dma input mode) 23 28 e5 pi12 in/out lv pio data [12] 1. mpeg header bit 14 C layer id (sdi mode) 2. data bit [0] (pio-dma input mode) 24 27 e6 sod (pi11) out lv serial output data 25 26 f7 soi (pi10) out lv serial output frame identification 26 25 d6 soc (pi9) out lv serial output clock 27 24 e7 pi8 in x start-up 1) : clock output scaler on / off out operation 2) : mpeg crc error 28 23 d7 xvdd supply x positive supply of output buffers 29 22 c6 xvss supply x ground of output buffers 30 21 c7 sid (pi7) in x serial input data 31 20 b6 sii (pi6) in vss serial input frame identification pin no. pin name type connection short description pmqfp 44-pin plcc 44-pin pbga 49-ball test alias in () (if not used)
mas 3507d preliminary data sheet 42 micronas 32 19 b7 sic (pi5) in x serial input clock 33 18 a7 pi4 in x start-up 1) : select sdi / pio-dma input mode out operation 2) : mpeg-frame sync 34 17 b5 pi3 in x start-up 1) : enable layer 3 / disable layer 3 decoding out operation 2) : mpeg header bit 20 (sampling frequency) 35 16 a6 pi2 in x start-up 1) : enable layer 2 / disable layer 2 decoding out operation 2) : mpeg header bit 21 (sampling frequency) 36 15 b4 pi1 in x start-up 1) : sdo: select 32-bit mode / 16-bit i 2 s mode out operation 2) : mpeg header bit 30 (emphasis) 37 14 a5 pi0 in x start-up 1) : select multimedia mode / broadcast mode out operation 2) : mpeg header bit 31 (emphasis) 38 13 c4 clko out lv clock output for the d/a converter 39 12 a4 pup out lv power up, i.e. status of voltage super- vision 40 11 b3 wsen in x enable dsp and start dc/dc con- verter 41 10 a3 wrdy out lv if wsen = 0: valid clock input at clki if wsen = 1: clock synthesizer pll locked 42 9 b2 avdd supply vdd supply for analog circuits 43 8 a2 clki in x clock input 44 7 a1 avss supply vss ground supply for analog circuits 1) start-up configuration see section 2.8. 2) not available in pio-dma mode, see section 2.8.1. pin no. pin name type connection short description pmqfp 44-pin plcc 44-pin pbga 49-ball test alias in () (if not used)
preliminary data sheet mas 3507d micronas 43 4.2.1. pin descriptions 4.2.1.1. power supply pins connection of all power supply pins is mandatory for the function of the mas 3507d. vdd supply vss supply the vdd/vss pair is internally connected with all digi- tal modules of the mas 3507d. xvdd supply xvss supply the xvdd/xvss pins are internally connected with the pin output buffers. avdd supply avss supply the avdd/avss pair is connected internally with the analog blocks of the mas 3507d, i.e. clock synthesizer and supply voltage supervision circuits. 4.2.1.2. dc/dc converter pins dcen in the dcen input signal enables the dc/dc converter operation. dcsg supply the dc converter signal ground pin is used as a basepoint for the internal switching transistor of the dc/dc converter. it must always be connected to ground. dcso out dcso is an open drain output and should be con- nected with external circuitry (inductor/diode) to start the dc/dc converter. when the dc/dc converter is not used, it has to be connected to vss. vsens in the vsens pin is the input for the dc/dc converter feedback loop. it must be connected directly with the schottky diode and the capacitor as shown in fig. 2C3. when the dc/dc converter is not used, it has to be connected to vdd. 4.2.1.3. control lines i2cc scl in/out i2cd sda in/out standard i 2 c control lines. normally there are pullup- resistors tied from each line to vdd. 4.2.1.4. parallel interface lines 4.2.1.4.1. pio handshake lines pio handshake lines are not used during start-up but in operation mode. read out of the status information and the demand mode work in m p-mode: set pcs = 0 and pr = 1. usage of pio-dma mode is possible with input mode via pio. pcs in the pio chip select must be set to 0 to activate the pio as output in operation mode (e.g. pi19 = demand signal in mutimedia mode & sdi input mode). pr in the pio pr must be set to 1 to validate data output from mas 3507d. rtw out rtw is not supported by the built-in firmware. rtr out rtr is only supported by the built-in firmware in pio- dma input mode. eod out end of dma (eod ) is only supported by the built-in firmware in pio-dma input mode. 4.2.1.4.2. pio data lines the function of the parallel interface is separated into two parts. during start-up, the pio will read the start- up configuration (independent from the pio hand- shake lines). this is done to define the environment for the mas 3507d (see section 2.8.1. for details). after start-up, the pio will be switched to m p-mode. with the pr = 1 and the pcs = 0, the pio interface is defined as output and displays some status informa- tion of the mpeg decoder. the pio can be connected to an external controller or to a display unit (e.g. led). the internal mpeg decoder firmware attaches specific functions to the following pins:
mas 3507d preliminary data sheet 44 micronas pi19 demand pin out when mas 3507d is in multimedia mode it demands w ith pi19 = 1 for new input data. pi18 mpeg-idex out pi17 mpeg-id out these pins mirror the according bits of the mpeg header (see table 2C9 for details). pi16 (sic*) in pi15 (sii*) in pi14 (sid* in the sic*, sid*, and sii* may be configured as alterna- tive serial input lines in order to support alternative serial digital inputs. pi13 layer id out pi12 layer id out these pins mirror the according bits of the mpeg header (see table 2C9 for details). pi8 mpeg-crc-error out/in the mpeg-crc-error pin is activated if no suc- cessful mpeg decoding is possible. the reason might be that the crc check of the mpeg frame header has detected an error or that no valid bit stream is available. the error signal will stay active for the entire duration of one mpeg frame. during start-up, this pin is an input for enabling/dis- abling the clko+divider (see section 3.6.). pi4 mpeg-frame-sync out/in the mpeg-frame-sync signal indicates that a mpeg header has been decoded properly and the internal mpeg decoder is in a synched state. the mpeg-frame-sync signal is inactive after power on reset and will be activated if a valid mpeg layer 2 or 3 header has been recognized. the signal will be cleared if the ancillary data information is read out by the controller via i 2 c interface. during start-up, this pin sets either sdi- or pio-dma- input mode (see section 3.6.). pi3 sampling frequency out pi2 sampling frequency out pi1 emphasis out pi0 emphasis out these pins mirror the according bits of the mpeg header (see table 2C9 for details). during start-up, these pins are input pins (see section 3.6.). 4.2.1.5. voltage supervision and other functions clki in this is the clock input of the mas 3507d. clki should be a buffered output of a crystal oscillator. standard clock frequency is 14.725. others can be used, if pll_offset register is changed by i 2 c. clko out the clko is an oversampling clock that is synchro- nized to the digital audio data (sod) and the frame identification (soi). pup out the pup output indicates that the power supply volt- age exceeds its minimal level (software adjustable). wsen in wsen enables dsp operation and starts dc/dc-con- verter. wrdy out wrdy has two functions depending on the state of the wsen signal. if wsen = 0, it indicates that a valid clock has been recognized at the clki clock input. if wsen = 1, the wrdy output will be set to 0 until the internal clock synthesizer has locked to the incom- ing audio data stream, and thus, the clko clock out- put signal is valid. 4.2.1.6. serial input interface sid in sii in sic in data, frame indication, and clock line of the serial input interface. the sii line should be connected with vss in the standard mode. 4.2.1.7. serial output interface sod out soi out soc out data, frame indication, and clock line of the serial out- put interface. the soi indicates whether the left or the right audio sample is transmitted. besides the two modes (selected by the pi1 during start-up), it is possi- ble to reconfigure the interface.
preliminary data sheet mas 3507d micronas 45 4.2.1.8. miscellaneous por in the power on reset pin is used to reset the digital parts of the mas 3507d. por is a low active signal. te in the te pin is for production test only and must be con- nected with vss in all applications. 4.2.2. pin configurations fig. 4C4: 44-pin plcc package fig. 4C5: 44-pin pmqfp package 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 avss clki avdd wrdy wsen pup clko pi0 pi1 pi2 pi3 dcso vsens pr pcs pi19 pi18 pi17 pi16 pi15 pi14 pi13 por i2cc i2cd vdd vss te dcen eod rtr rtw dcsg sic sii sid xvss xvdd pi4 pi8 soc soi sod pi12 mas 3507d 34 35 36 37 38 39 40 41 42 43 44 22 21 20 19 18 17 16 15 14 13 12 1234567891011 33 32 31 30 29 28 27 26 25 24 23 pi3 pi2 pi1 pi0 clko pup wsen wrdy avdd clki avss pi13 pi14 pi15 pi16 pi17 pi18 pi19 pcs pr vsens dcso sic sii sid xvss xvdd pi4 pi8 soc soi sod pi12 por i2cc i2cd vdd vss te dcen eod rtr rtw dcsg mas 3507d
mas 3507d preliminary data sheet 46 micronas 4.2.3. internal pin circuits fig. 4C6: input pins pcs , pr fig. 4C7: input pin te, dcen fig. 4C8: input pins wsen, por fig. 4C9: input pin clki fig. 4C10: input/output pins pi0...pi4, pi8, soc, soi, sod, pi12.. . pi19 fig. 4C11: input/output pins i2cc, i2cd fig. 4C12: input/output pins dcso, dcsg fig. 4C13: output pins wrdy, rtw , eod , rtr , clko, pup fig. 4C14: input pin vsens fig. 4C15: input/output pins sic, sii, sid ttlin vdd p n vss vdd n vss dcso dcsg vss vdd vss n p vss vsens vdd p n vss
preliminary data sheet mas 3507d micronas 47 4.2.4. electrical characteristics 4.2.4.1. absolute maximum ratings stresses beyond those listed in the absolute maximum ratings may cause permanent damage to the device. this is a stress rating only. functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions/characteristics of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 4.2.4.2. recommended operating conditions symbol parameter pin name min. max. unit t a ambient operating temperature - 30 85 c t s storage temperature - 40 125 c p max power dissipation vdd, xvdd, avdd 600 400 (pbga) mw v sup supply voltage vdd, xvdd, avdd 5.5 v v idig input voltage, all digital inputs - 0.3 v sup +0.3 v i idig input current, all digital inputs - 20 +20 ma i out current, all digital output 0.5 a i outdc current dcso 1.5 a symbol parameter pin name min. typ. max. unit t a ambient temperature range - 30 85 c v sup supply voltage vdd, xvdd, avdd 2.5 2.7 3.6 v reference frequency generation clk f clock frequency 1) clki 14.725 mhz clk i_v clock input voltage 0 v sup v clk amp clock amplitude 0.5 v pp 1) range acc. to section 3.7.2.1.
mas 3507d preliminary data sheet 48 micronas levels i il27 input low voltage @v sup = 2.5 v ... 3.6 v por i2cc, i2cd, dcen, wsen 0.4 v i ih36 input high voltage @v sup = 2.5 v ... 3.6 v 1.8 v i ih33 input high voltage @v sup = 2.5 v ... 3.3 v 1.7 v i ih30 input high voltage @v sup = 2.5 v ... 3.0 v 1.6 v i ild input low voltage pi 2) , sii, sic, sid, pr, pcs, te, 0.4 v i ihd input high voltage v sup - 0.5 v t rf rise / fall time of digital inputs pi, sii, sic, sid, pr, pcs, clki 10 ns d cycle duty cycle of digital clock inputs sic, clki 40 50 60 % dc-dc converter external circuitry c 1 blocking capacitor (25 m w esr) 3) vsens, dcsg 330 m f v f schottky diode forward voltage 4) dcso, vsens 0.35 0.45 v l inductance of ferrite ring core coil 5) (50 m w ),vac 616/103 dcso 20 m h 2) i = 0 to 4, 8 , 12 to 19 3) sanyo oscon 6sa330m (distributed by endrich bauelemente, d-72202 nagold-lselshausen, www.endrich.com) 4) zetex zmcs1000 (distributed by zetex, d-81673 mnchen, europe.sales@zetex.com ) , standard schottky 1n5817 5) c8 r/4l, sds0604 (distributed by endrich bauelemente, see above) symbol parameter pin name min. typ. max. unit
preliminary data sheet mas 3507d micronas 49 4.2.4.3. characteristics at t a = - 30 to 85 c, v sup = 2.5 to 3.6 v, typ. values at t a = 27c, v sup =2.7v, clk f = 14.725 mhz, duty cycle = 50% symbol parameter pin name min. typ. max. unit test conditions supply voltage i sup current consumption vdd, xvdd, avdd 32 ma 2.7 v, sampling frequency 3 32khz 17 ma 2.7 v, sampling frequency 24 khz 11 ma 2.7 v, sampling frequency 12 khz digital outputs and inputs v dol output low voltage soi 1) , soc 1) , sod 1) , eod, rtr , rtw , wrdy, pup, clko pi 0.3 v i load =6ma v dih output high voltage v sup - 0.3 vi load =6ma z digi input impedance pi, sii, sic, sid, pr, pcs, clki 7pf i dleak digital input leakage current - 11 m a0v mas 3507d preliminary data sheet 50 micronas 4.2.4.3.1. i 2 c characteristics at t a = - 30 to 85 c, v sup =2.5 to 3.6 v, typ. values at t a =27c, v sup =2.7v, clk f = 14.725 mhz, duty cycle = 50 % fig. 4C16: i 2 c timing diagram symbol parameter pin name min. typ. max. unit test conditions r on output resistance i2cc, i2cd 60 w i load =5ma, v sup =2.7v f i2c i 2 c bus frequency i2cc 400 khz t i2c1 i 2 c start condition setup time i2cc, i2cd 300 ns t i2c2 i 2 c stop condition setup time i2cc, i2cd 300 ns t i2c3 i 2 c clock low pulse time i2cc 1250 ns t i2c4 i 2 c clock high pulse time i2cc 1250 ns t i2c5 i 2 c data hold time before rising edge of clock i2cc 80 ns t i2c6 i 2 c data hold time after falling edge of clock i2cc 80 ns v i2col i 2 c output low voltage i2cc, i2cd 0.3 v i load =5ma i i2coh i 2 c output high leakage current i2cc, i2cd 1uav i2ch =3.6v t i2col1 i 2 c data output hold time after falling edge of clock i2cc, i2cd 20 ns t i2col2 i 2 c data output setup time before rising edge of clock i2cc, i2cd 250 ns f i2c =400khz i2cc i2cd as input i2cd as output t i2c1 t i2c5 t i2c6 t i2c2 t i2c4 t i2c3 1/f i2c t i2col2 t ic2ol1 h l h l h l
preliminary data sheet mas 3507d micronas 51 4.2.4.3.2. i 2 s bus characteristics C sdi at t a = - 30 to 85 c, v sup =2.5 to 3.6 v, typ. values at t a =27c, v sup =2.7v, clk f = 14.725 mhz, duty cycle = 50 % fig. 4C17: serial input symbol parameter pin name min. typ. max. unit test conditions t siclk i 2 s clock input clockperiod sic 960 ns multimedia mode, mean data rate < 150 kbit/s t siids i 2 s data setuptime before falling edge of clock sic, sid 50 t siclk - 100 ns t siidh i 2 s data hold time sid 50 ns t bw burst wait time sic, sid 480 h l h l h l sic (sii) sid t siclk t siidh t siids
mas 3507d preliminary data sheet 52 micronas 4.2.4.3.3. i 2 s characteristics C sdo at t a = - 30 to 85 c, v sup = 2.5 to 3.6 v, typ. values at t a =27c, v sup =2.7v, clk f = 14.725 mhz, duty cycle = 50 % fig. 4C18: serial output symbol parameter pin name min. typ. max. unit test conditions t soclk i 2 s clock output period soc 325 ns 48 khz stereo 32 bit/sample t soiss i 2 s wordstrobe hold time after falling edge of clock soc, soi 10 t soclk / 2 ns t soodc i 2 s data hold time after falling edge of clock soc, sod 10 t soclk / 2 ns h l h l h l soc soi sod t soclk t soiss t soiss t soodc
preliminary data sheet mas 3507d micronas 53 4.2.4.4. firmware characteristics at t a = - 30 to 85 c, v sup = 2.5 to 3.6 v, typ. values at t a =27c, v sup =2.7v, clk f = 14.725 mhz, duty cycle = 50 % 4.2.4.4.1. input timing parameters of the multimediamode fig. 4C19: demand mode t sdstart refers to the maximal response time for a serial data source to start data transmission with respect to the ris- ing edge of the demand signal at the pin pi19. t sdstop refers to the maximal response time for a serial data source to stop data transmission with respect to the fall- ing edge of the demand signal at the pin pi19. symbol parameter min. typ. max. unit test conditions synchronization times t mpgsync synchronization on mpeg bit streams 12...36 72 ms f s =32khz, mpeg2.5 ranges pllrange tracking range of sampling clock recovery pll - 200 200 ppm broadcast mode symbol parameter pin name min. typ. max. unit test conditions t sdstart reaction time for data source pi19 3.1 5.7 ms f s =48khz, 320...64 kbit/s t sdstart reaction time for data source 4.2 9.2 ms f s =24khz, 320...32 kbit/s t sdstar reaction time for data source 23.1 25.6 ms f s =12khz, 64...16 kbit/s t sdstar reaction time for data source 34.8 38.4 ms f s =8khz, 64...8 kbit/s t sdstop reaction time for data source 1.3 ms h l t sdstart t sdstop pi19
mas 3507d preliminary data sheet 54 micronas 4.2.4.5. dc/dc converter characteristics at t a = - 30 to 85 c, v sup =3.0v, clk f =14.725mhz, f sw = 230 khz, typ. values at t a =+27c all measurements are made with a c8 r/4l 20 m h, 25 m w ferrite ring-core coil, zetex zlmcs1000 schottky diode, and sanyo/oscon 6sa330m 330 m f, 2 5 m w esr capacitors at input and output (see section 4.2.4. on page 47). symbol parameter pin name min. typ. max. unit test conditions v in1 minimum start-up input voltage 0.9 1.0 v i load =0ma dccf = $08000 (reset) v in2 minimum operating voltage 0.6 0.8 v i load =55ma, dccf = $08000 (reset) 1.3 1.8 v i load = 250 ma, dccf = $08000 (reset) v out output voltage 2.0 1) 3.5 v see section 4.2.4.6. dv out /dv in / v out line regulation 1 % v in = 1.0...3.0 v, i load =55ma dv out /di load / v out load regulation 0.6 % v in =1.2v, i load = 0...55 ma, f sw =230khz dv out /di load / v out load regulation 1.2 % v in =1.2v, i load = 0...55 ma, f sw = 165 khz h max maximum efficiency 90 % i supply supply current 1.1 5 ma v in = 3.0 v, i load =0, includ. switch current i l,max inductor current limit dcso, dcsg 1.0 1.4 a r on switch on-resistance dcso, dcsg 0.2 0.4 w t j =25 c i leak switch leakage current dcso, dcsg 0.1 1 m at j =25 c f sw switch frequency dcso, dcsg 156 230 460 khz depending on dccf t start start up time to pup-enable dcen , pup 8msv in =1.0v, i load =1ma, puplim = 010 (reset) v starttran start-up to normal mode transition voltage vsense 1.9 v 1) see section 4.2.4.2.
preliminary data sheet mas 3507d micronas 55 4.2.4.6. typical performance characteristics fig. 4C20: efficiency vs. load current load current (a) 0 20 40 60 80 100 efficiency (%) efficiency vs. load current (vout=2.7v) load current (a) 0 20 40 60 80 100 efficiency (%) efficiency vs. load current (vout=3.5v) load current (a) 0 20 40 60 80 100 efficiency (%) efficiency vs. load current (vout=2.2v) load current (a) 0 20 40 60 80 100 efficiency (%) efficiency vs. load current (vout=3.0v) 10 10 10 10 1 -4 -3 -2 -1 10 10 10 10 1 -4 -3 -2 -1 10 10 10 10 1 -4 -3 -2 -1 10 10 10 10 1 -4 -3 -2 -1 vin: 2.4v 1.8v 1.5v 1.2v 0.9v 0.7v vin: 3.0v 2.4v 1.8v vin: 2.4v 1.8v 1.2v vin: 1.5v 1.2v 0.9v 0.7v 3.0 v 1.8 v vin 0.7 v 2.4 v vin 0.7 v 1.5 v vin 2.4 v 1.2 v vin
mas 3507d preliminary data sheet 56 micronas fig. 4C21: output voltage vs. input voltage fig. 4C22: output voltage vs. load current 1.5 2 2.5 3 3.5 input voltage (v) 2.6 2.8 3 3.2 3.4 3.6 output voltage (v) output voltage vs. input voltage iload=250ma 0.9 1.4 1.9 2.4 2.9 input voltage (v) 2 2.2 2.4 2.6 2.8 3 3.2 output voltage (v) output voltage vs. input voltage iload=50ma 3.5 v 3.1 v 2.7 v 3.1 v 2.2 v 2.7 v 0 0.1 0.2 0.3 load current (a) 2.6 2.8 3 3.2 3.4 3.6 output voltage (v) output voltage vs. load current 0 0.02 0.04 0.06 0.08 load current (a) 2 2.2 2.4 2.6 2.8 3 3.2 3.4 output voltage output voltage vs. load current vin=3v, 2.4v, 1.8v vin=2.4v vin=1.5v, 0.9v vin=1.5v, 0.9v vin vin vin
preliminary data sheet mas 3507d micronas 57 fig. 4C23: maximum load current vs. input voltage fig. 4C24: no load supply current vs. input voltage 0 1 2 3 input voltage (v) 0 0.2 0.4 0.6 0.8 maximum load current (a) maximum load current vs. input voltage vout= 3.5v 3.1v 2.7v 2.2v 3.5v 2.2v v out 0 1 2 3 input voltage (v) 0 2.0 4.0 6.0 no load supply current (ma) no load supply current vs. input voltage v out =3v
mas 3507d preliminary data sheet 58 micronas fig. 4C25: load transient-response fig. 4C26: line transient-response fig. 4C27: startup waveform 500.00 m s/div v in = 1.2 v; v out =3v 1 load current 200.0 ma/div 2 output voltage 100.0 mv/div / ac-coupled 3 inductor current 500.0 ma/div 3v 0a 0a i load =100ma; v out =3v 1v in 2.000 v/div 2 output voltage 50.00 mv/div / ac-coupled 3 inductor current 200.0 ma/div 5.00 ms/div 3v 2v 200 ma v in =1v; i load =0ma 1 v (dcen) 2.000 v/div 2 v (pup) 2.000 v/div 3 inductor current 500.0 ma/div 4 output voltage 2.000 v/div 500 m s/div 0a 3v 3v 3v
preliminary data sheet mas 3507d micronas 59
all information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. any new issue of this data sheet invalidates previous issues. product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples deliv- ered. by this publication, micronas gmbh does not assume responsibil- ity for patent infringements or other rights of third parties which may result from its use. further, micronas gmbh reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. no part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of micronas gmbh. mas 3507d preliminary data sheet 60 micronas micronas gmbh hans-bunte-strasse 19 d-79108 freiburg (germany) p.o. box 840 d-79008 freiburg (germany) tel. +49-761-517-0 fax +49-761-517-2174 e-mail: docservice@micronas.com internet: www.micronas.com printed in germany order no. 6251-459-3pd 5. data sheet history 1. preliminary data sheet : mas 3507d mpeg 1/2 layer2/3 audio decoder, feb. 25, 1998, 6251-459-1pd. first release of the preliminary data sheet. 2. preliminary data sheet: mas 3507d mpeg 1/2 layer 2/3 audio decoder, oct. 21, 1998, 6251-459-2pd. second release of the preliminary data sheet. major changes: C table 3C20: volume matrix conversion added C address for prefactor register corrected C definition for register $aa changed C fig. 4C1: outline dimension for plcc44 changed C fig. 4C2: pqfp44 package diagram changed C fig. 4C3 and fig. 4C4: pin configurations added 3. preliminary data sheet: mas 3507d mpeg 1/2 layer 2/3 audio decoder, march 16, 2000, 6251-459-3pd. third release of the preliminary data sheet.

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